In recent years, semiconductor devices in which an IC chip including, for example, a semiconductor integrated circuit, is mounted on a substrate have been used in various electronic devices. For example, since IC chips, such as application specific integrated circuit (ASIC) chips and field-programmable gate array (FPGA) chips, have integrated functions, the IC chips include a large number of input/output terminals. Such IC chips including a large number of input/output terminals adopt a terminal array configuration in which terminals are arranged in a matrix, in order to reduce the mounting area. An example of such IC chips is an IC chip including memory such as dynamic random access memory (DRAM). Not only data input/output signals but a reference voltage used for the memory is also applied to the IC chip including memory. The reference voltage is used in the memory as a threshold for determining whether a signal voltage is at high level or low level. Thus, fluctuations of the reference voltage caused by, for example, noise causes malfunction of the memory chip. Furthermore, when comparing the signal voltage and the reference voltage in the memory, a current caused by the signal voltage flows as noise into an interconnection used for reference voltage supply, every time the signal voltage swings. Therefore, a countermeasure against an adverse effect of noise on the reference voltage becomes particularly important. In view of this, a configuration in which a capacitor is connected between a terminal of the IC chip to which the reference voltage is applied and a patterned ground conductor has been adopted in order to reduce noise contained in the reference voltage. With this configuration, when there is an increase in the distance between the capacitor and the terminal of the IC chip to which the reference voltage is applied, the impedance of the interconnection between the IC chip and the capacitor increases. As a result, the noise reduction effect brought about by the capacitor is reduced.
In view of this, a technique has been proposed for mounting a capacitor on the back surface of a substrate opposite a main surface thereof on which an IC chip is mounted, and connecting the IC chip and the capacitor via a via interconnection (see Patent Literature 1, for example). This is in an attempt to reduce the impedance of the interconnection between the IC chip and the capacitor by reducing the distance between the IC chip and the capacitor.